1. Technical Field
The present invention relates to a semiconductor device provided with a partially depleted transistor in a semiconductor layer on an insulating layer and a manufacturing method of the semiconductor device.
2. Related Art
The development and practical application of a technology of forming a semiconductor device in a thin semiconductor film formed on an insulating film (silicon on insulator (SOI)) are underway for a low-power semiconductor device in the next generation. The SOI has advantages such as a high ON/OFF ratio or steep subthreshold characteristic of a drain current, low noise, and a low parasitic capacitance, and the application thereof to integrated circuits used for watches, mobile devices, and the like is underway. At present, a metal insulator semiconductor field effect transistor (MISFET) having an SOI structure is used for various semiconductor integrated circuits. Especially a MISFET having a partially depleted (PD) SOI structure (hereinafter referred to as a PD-SOI MISFET) that can be manufactured easily in the same manner as the manufacturing method of a MISFET having a bulk structure in the related art is widely applied to semiconductor products. The structure of the PD-SOI MISFET is disclosed in, for example, JP-A-2004-128254.
In the PD-SOI MISFET, a body region is electrically isolated from other regions by means of an element isolation film and an insulating layer (also referred to as a BOX layer), and the potential of the body region (that is, a body potential) floats. Therefore, the influence of a phenomenon called a substrate floating effect on device characteristics (for example, a history effect) has to be considered. The history effect is a phenomenon in which a body potential and a drain current fluctuate due to the history of voltage having been applied to a gate, a drain, and a source, causing unstable device characteristics.
The history effect can be suppressed by a known body potential fixing method shown in, for example, FIGS. 10A and 10B.
FIGS. 10A and 10B are a plane view and a cross-sectional view showing a configuration example of a PD-SOI MISFET 90 according to the related art. As shown in FIGS. 10A and 10B, the PD-SOI MISFET 90 has a gate insulating film 93 formed on the surface of an SOI layer 92 on a BOX layer 91, a gate electrode 94 formed above the SOI layer 92 via the gate insulating film 93, an N-type source 95a or drain 95b formed in the SOI layer 92 below both sides of the gate electrode 94, and a P-type impurity layer 96 connected to the SOI layer 92 in a region just below the gate electrode 94 (that is, a body region).
In the PD-SOI MISFET 90, a depletion layer 92a does not reach the BOX layer 91, and a neutral region 92b is left, during its operation as shown in FIG. 10B. Since the potential of the body region 92 (that is, a body potential) is fixed to a desired potential (for example, a ground potential) via a contact 97 and the P-type impurity layer 96, the substrate floating effect is suppressed, and the history effect is suppressed. Such a structure is called body contact, or also called body tie, which is disclosed in, for example, JP-A-2004-119884. In FIG. 10A, the inter-layer insulating film 98 shown in FIG. 10B is omitted for avoiding complication of the drawing.